@inproceedings{
MRAM:HLK+04,
   Author = {Ha, Y. K. and et al.},
   Title = {{MRAM with Novel Shaped Cell Using Synthetic Anti-Ferromagnetic Free Layer}},
   BookTitle = {Symposium on VLSI Technology},
   Pages = {24-25},
   Abstract = {Magnetic random access memory (MRAM) with magnetic tunnel junction (MTJ) using synthetic anti-ferromagnetic (SAF) free layers of various shapes has been developed. SAF free layers show the predominance in the scalability compared with a conventional single free layer. It is also revealed that a novel shaped MTJ with a SAF free layer has a remarkably large writing margin.},
   Keywords = {antiferromagnetism
magnetic multilayers
magnetic storage
magnetic tunnelling
random-access storage
magnetic random access memory
magnetic tunnel junction
synthetic antiferromagnetic free layer},
   Year = {2004} }



@inproceedings{
MRAM:HYY+05,
   Author = {Hosomi, M. and et al.},
   Title = {{A novel nonvolatile memory with spin torque transfer magnetization switching: spin-ram}},
   BookTitle = {International Electron Devices Meeting},
   Pages = {459-462},
      Year = {2005} }

  @inproceedings{
MRAM:NEC09,
   Author = {Hoding, R.},
   Title = {{NEC develops 32 Megabit MRAM for embedded SoCs }},
   BookTitle = {EETimes, Feb. 12},
      Year = {2009} }  

@inproceedings{
MRAM:KTM+07,
   Author = {Kawahara, T. and et al.},
   Title = {{2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read}},
   BookTitle = {IEEE International Solid-State Circuits Conference},
   Pages = {480-617},
   Abstract = {A 1.8V 2Mb spin-transfer torque RAM chip using a 0.2mum logic process with an MgO tunneling barrier cell demonstrates the circuit technologies for potential low-power non-volatile RAM, or universal memory. This chip features an array scheme with bit-by-bit bidirectional current write to achieve proper spin-transfer torque writing in 100ns, and parallelizing-direction current reading with a low-voltage bit-line that leads to 40ns access time.},
   Keywords = {logic circuits
low-power electronics
magnesium compounds
random-access storage
tunnelling
0.2 micron
1.8 V
100 ns
2 Mbit
40 ns
MgO
bit-by-bit bidirectional current write
logic process
low-power nonvolatile RAM
parallelizing-direction current read
spin-transfer torque RAM
tunneling barrier cell
universal memory},
   Year = {2007} }



@inproceedings{
MRAM:MYO+04,
   Author = {Motoyoshi, M. and et al.},
   Title = {{A study for 0.18 um high-density MRAM}},
   BookTitle = {Symposium on VLSI Technology},
   Pages = {22-23},
   Abstract = {In this paper, we study to reduce the switching dispersion and improve 0/1 separation of Magnetic Tunnel Junction (MTJ) elements in order to realize high density MRAM. Various kinds of MTJ sizes and shapes have been evaluated and conclude that in ellipse like shape pattern aspect ratio more than 2 is enough for reproducing and reliable switching characteristics. As regards the reading characteristics, the combination of the optimized MTJ pattern and process makes 21.4 sigma separation between high and low resistance states. In further study of the relation between MTJ shapes and switching distribution, we found a "Saturn" shaped MTJ has best switching behavior. Also the toggle mode MRAM is evaluated and its effectiveness for high speed programming is confirmed.},
   Keywords = {CMOS integrated circuits
magnetic tunnelling
random-access storage
0.18 /spl mu/m high-density MRAM
0.18 micron
Magnetic Tunnel Junction
ellipse like shape pattern aspect ratio
switching dispersion},
   Year = {2004} }



@inproceedings{
MRAM:TTO+06,
   Author = {Tanizaki, Hiroaki and et al.},
   Title = {{A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme}},
   BookTitle = {IEEE Asian Solid-State Circuits Conference },
   Pages = {303-306},
   Abstract = {A high-density and high-speed memory cell named 1-Transistor 4-Magnetic Tunnel Junction (1T-4MTJ) has been proposed for Magnetic Random Access Memory (MRAM). The new 1T-4MTJ cell has been successfully demonstrated by a 1Mb MRAM test device, using a 130nm CMOS process. The sensing scheme of a Self-Reference Sense amplifier with Voltage offset (SRSV) enables high-speed memory operation (access time) of tAC=56nsec and 50MHz@4cycle.},
      Year = {2006} }



@inproceedings{
MRAM:ZBM+06,
   Author = {W. Zhao and et al.},
   Title = {{Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid Magnetic-CMOS design}},
   BookTitle = {IEEE International Behavioral Modeling and Simulation Workshop},
   Pages = {40-43},
   Abstract = {The development of hybrid magnetic-CMOS circuits such as MRAM (magnetic RAM) and magnetic logic circuit requires efficient simulation models for the magnetic devices. A macro-model of magnetic tunnel junction (MTJ) is presented in this paper. This device is the most commonly used magnetic components in CMOS circuits. This model is based on spin-transfer torque (STT) writing approach. This very promising approach should constitute the second generation of MRAM switching technology; it features small switching current (~120uA) and high programming speed (&lt;1ns). The macro-model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform with Spectre 5.0.32 simulator. Many experimental parameters are integrated in this model to improve the simulation accuracy. So, the model can efficiently be used to design hybrid magnetic CMOS circuits},
   Keywords = {CMOS memory circuits
circuit simulation
hardware description languages
integrated circuit design
integrated circuit modelling
magnetic storage
magnetic switching
magnetic tunnelling
random-access storage
Cadence Virtuoso platform
Spectre 5.0.32 simulator
Verilog-A language
hybrid magnetic-CMOS circuit design
magnetic RAM switching technology
magnetic device
magnetic logic circuit
spin-transfer torque based magnetic tunnel junction device macro-model
spin-transfer torque writing approach},
   Year = {2006} }

@inproceedings{
MRAM:ITRS07,
   Author = {},
   Title = {{International Technology Roadmap for Semiconductor}},
   BookTitle = {},
   Pages = {},
   Year = {2007} }


@inproceedings{
MRAM:BMN+06,
   Author = {Black Brian and et al.},
   Title = {{Die Stacking (3D) Microarchitecture}},
   BookTitle = {International Symposium on Microarchitecture },
   Pages = {469-479},
   Abstract = {3D die stacking is an exciting new technology that increases transistor density by vertically integrating two or more die with a dense, high-speed interface. The result of 3D die stacking is a significant reduction of interconnect both within a die and across dies in a system. For instance, blocks within a microprocessor can be placed vertically on multiple die to reduce block to block wire distance, latency, and power. Disparate Si technologies can also be combined in a 3D die stack, such as DRAM stacked on a CPU, resulting in lower power higher BW and lower latency interfaces, without concern for technology integration into a single process flow. 3D has the potential to change processor design constraints by providing substantial power and performance benefits. Despite the promising advantages of 3D, there is significant concern for thermal impact. In this research, we study the performance advantages and thermal challenges of two forms of die stacking: Stacking a large DRAM or SRAM cache on a microprocessor and dividing a traditional micro architecture between two die in a stack},
   Keywords = {DRAM chips
SRAM chips
logic design
microprocessor chips
3D die stacking microarchitecture
DRAM cache
SRAM cache
microprocessor chip},
   Year = {2006} }
